RISC-V server chip designer Ventana Micro Systems has pushed out its second generation Veyron processor, squeezing in more cores and the ability for customers to add custom accelerator bits to a bespoke system-on-chip (SoC) blueprint.

Ventana launched its first generation kit, the Veyron V1, at last year’s RISC-V Summit, targeting customers seeking a datacenter-class processor that could claim performance comparable to other architectures on the market.

The Cupertino RISC-y slinger chiefly sells its product in the form of a ready-made multi-core chiplet, with the idea that customers such as hyperscalers can combine multiple chiplets in an SoC to meet their specific processing requirements.

According to Travis Lanier, Ventana’s VP of marketing & product, the Veyron V2 incorporates all of the updates in the RISC-V specifications, as well as aligning with Universal Chiplet Interconnect Express (UCIe) as the standard for connecting chiplets together, rather than the Bunch of Wires (BoW) system seen in the V1.

Veyron V2 supports the RVA23 feature set, which is the RISC-V instruction set profile for this year, and implements the RISC-V Input-Output Memory Management Unit (IOMMU) specifications.

The IOMMU specification being ratified “was a big deal in the RISC-V space,” according to Lanier. “Anytime you have a virtual machine, and you want to have direct access to one of your PCIe devices, you don't have to do all the software overhead to switch it around, so this is a critical feature for datacenter applications,” he explained.

It is also a key part of RISE compatibility, he claimed, which is an industry project aimed at building the necessary application ecosystem around RISC-V.

Ventana has also taken advantage of the RISC-V Vector Extension specifications to add a vector processing unit to its cores. This is 512 bits wide, and also features what Ventana calls AI Matrix Extensions, which Lanier claimed will “help significantly with some of those generative AI or inference workloads.”

In addition, each Veyron V2 chiplet now supports up to 32 cores instead of 16 in the previous generation, while the clock speed and the overall number of cores remain at 3.6GHz and up to 192 cores. The size of the caches has also increased, to 1MB of L2 per core and up to 128MB of shared cluster-level L3 cache.

All of the changes in Veyron V2 translate to a performance increase of almost 40 percent over the previous generation, Lanier claimed.

Pedal to the metal

Veyron V2 also supports DSA, or Domain Specific Acceleration, a capability that allows the customer to add bespoke accelerator chiplets to their SoC. This is aimed at hyperscale customers that may wish to boost specific workloads in the datacenter, according to Lanier, such as compression and encryption, TCP offload processing in networks, or key/value processing in databases.

These accelerator chiplets are supported by the Veyron cores via custom instructions that Ventana has added, which is one of the supposed big selling points of the whole RISC-V architecture.

In this case, the custom instructions enable software to call the accelerator, in what could be seen as an echo of the way Intel processors had instructions to call the floating point unit (FPU) back in the days when one of these was an optional separate chip.

Another claim for Veyron V2 is that it has been designed to be more resistant to side channel attacks, such as the Spectre and Meltdown flaws that potentially allowed data to be stolen from a server’s memory.

Lanier was cagey about specifically what this means, but emphasized that it does not mean such an attack is impossible with Veyron chips, just that the V2 has been designed with knowledge of the way these attacks are carried out.

“We had the luxury of starting our design, after all these came to light,” he said, adding that the cost to datacenter customers of running software patches or mitigations to affected servers can often be a 10 or even 20 percent hit on performance.

The Veyron V2 silicon is planned to be available sometime in the second half of 2024.

With last year’s V1, the chiplets were manufactured by TSMC using a 5nm production node. This year, Ventana is not specifying which foundry is producing the V2 chiplets, but said they will be made using a process smaller than 5nm. ®

https://www.theregister.com//2023/11/07/ventana_riscv_server/