Analysis Arm might not think RISC-V is a threat to its newfound foothold in the datacenter, but growing pressure on Chinese chipmaking could ultimately change that, Forrester Research analyst Glenn O'Donnell tells The Register.

Over the past few years the US has piled on export bans and trade restrictions on Chinese chipmakers in an effort to stall the country's semiconductor industry. This has included barring companies with ties to the Chinese military from purchasing x86 processors and AI kit from the likes of Intel, AMD, and Nvidia.

"Because the US-China trade war restricts x86 sales to China, Chinese infrastructure vendors and cloud providers need to adapt to remain in business," O'Donnell said. "They initially pivoted to Arm, but trade restrictions exist there too. Chinese players are showing great interest in RISC-V."

RISC-V provides China with a shortcut around the laborious prospect of developing their own architecture. "Coming up with a whole new architecture is nearly impossible," O'Donnell said. But "a design based on some architecture is very different from the architecture itself." 

So it should come as no surprise that the majority of RISC-V members are based in China, according to a report published last year. And the country's government-backed Chinese Academy of Sciences is actively developing open source RISC-V performance processors.

Alibaba's T-Head, which is already deploying Arm server processors and smartNICs, is also exploring RISC-V-based platforms. But for now, they're largely limited to edge and IoT appliances. However, O'Donnell emphasizes that there is no technical reason that would prevent someone from developing a server-grade RISC-V chip.

"Similar to ARM, many people dismiss RISC-V as underpowered for more demanding applications. They are wrong. Both are architectures, not specific designs. As such, one can design a powerful processor based on either architecture," he said.

Google RISC-ifies the TPU

It's not just China that stands to benefit from RISC-V's open and extensible nature. "I can see niche applications by cloud providers who can adapt the software layers to make the underlying processor largely invisible," O'Donnell said.

One recent example is Google's Tensor processing unit (TPU). Earlier this month, the search giant disclosed it was working with RISC-V chip designer SiFive to integrate the open source ISA into its TPU.

Google's TPUs are specifically designed to accelerate machine learning workloads written in TensorFlow. The accelerator is essentially a big bfloat matrix math engine — Google calls these MXUs — with some high-bandwidth memory and a few CPU cores to make it programmable.

It's the latter component that SiFive's roughly year-long collaboration with Google has focused much of its attention on, explained Jack Kang, SVP of business development at SiFive, in an interview with The Register.

Essentially, Google provides the big, powerful matrix-math crunching engines and SiFive's X280 processor provides the other bits necessary to do anything interesting with it. The idea here is users can interact with a TPU as if it were just another accelerator block baked into a RISC-V core. "It just looks like an X280," Kang said.

RISC-V drives in the datacenter

During a press conference to announce its second-generation Neoverse V2 core architecture earlier this month, Arm executives downplayed the risk of the open source ISA to their chip empire.

"We really don't see RISC-V as a significant competitor to us in the datacenter space right now, or in the near future," said Chris Bergey, SVP and GM of Arm's Infrastructure business, characterizing the rival ISA as being best suited to niche applications.

While there might not be a RISC-V chip capable of going toe-to-toe with the Arm Neoverse cores that power Amazon's Graviton or Ampere's Altra chips just yet, that doesn't mean RISC-V isn't making inroads in the datacenter in other ways.

One of the most attractive things about RISC-V over Arm is the relatively low cost of building chips based on the tech, especially for highly commoditized use cases like embedded processors, O'Donnell explained. While nowhere as glamorous as something like a server CPU, embedded applications are one of RISC-V's first avenues into the datacenter.  

Essentially every peripheral that plugs into a server has a small computer built into it. Take the storage controllers and other microprocessors baked into hard drives. These control the movement of the magnetic heads as they dance across the platters reading and writing data. We've seen similar developments around SSD controllers as well.

Several hard drive manufacturers have committed to transitioning their embedded processors to RISC-V. Western Digital says it has developed four RISC-V processors for use in a variety of products, while Seagate says it's working on two chips to replace the Arm processors it has traditionally relied on for its storage kit.

These embedded applications are where O'Donnell expects RISC-V will see widespread adoption, including in the datacenter. Whether the open source ISA will rise to the level of Arm or x86 is another matter entirely.

"Can they design a high-performance processor around the RISC-V architecture? Yeah. I think we're seeing some evidence of that," he said. "I haven't seen any evidence that it has performance on par with x86 from Intel or AMD, or even the M1 chip from Apple."

But if the US pressure campaign on the Chinese semiconductor industry continues unabated, it would only take one competitive chip to prove it's possible, O'Donnell explained. "Once someone proves it can be done, it opens the gates."

"If China got really serious about this, we could have a truly viable third architecture to contend with." ®