Akeana, which has secured over $100 million in funding over the past few years, has now launched its long-awaited lineup of RISC-V CPU designs, which are aimed at applications from embedded to datacenter systems.

With this launch, Akeana feels it's ready to challenge both RISC-V peers and Arm.

Ever since it was founded in 2021 by former Marvell employees (two of them at Cavium before it was acquired by Marvell), Akeana has been tight-lipped about its development of RISC-V chips and was in stealth mode. But three years and over a hundred million dollars later, the startup has finally revealed and launched its RISC-V blueprints, available to license, and claims that it will challenge "the semiconductor industry status quo" set by Arm, SiFive, Andes, and others.

Behind those fighting words are three RISC-V CPU cores, a variety of chip building blocks, and its AI Matrix computation engine, which Akeana says can handle matrix multiplication operations in machine-learning workloads.

The fabless firm's 100 Series CPUs are 32-bit and are intended to be used in embedded system-on-chips and microcontrollers for edge devices. The higher-end 1000 Series offers 64-bit cores paired with a memory management unit, in- and out-of-order pipelines, multi-threading, vector extensions, and optionally AI extensions.

Perhaps most interesting are Akeana's 5000 Series cores, which are 64-bit and essentially big versions of the 1000 Series cores that only do out-of-order instructions, and are specifically designed for high-performance applications such as PCs and datacenter boxes. Akeana boasts that these cores have "much higher" single-threaded prowess than the 1000 Series, though didn't provide any specific figures. 

The firm envisions laptop chips could use 1000 and 5000 Series cores together for a big-little or hybrid design, a strategy that Apple, Intel, AMD, and Qualcomm all employ.

Each Series product stack offers three or four variants, ranging in instruction dispatch configuration, cache size, pipeline stages, and other characteristics. Clusters can have up to eight cores each, but it's not clear what the limit on cores and clusters are for a single chip, and how good scaling is. We guess it's still early days.

Akeana's IP blocks for building systems-on-chip (SoCs) include a coherent cluster cache and I/O MMU, plus scalable mesh and coherence hub tech primarily intended for use in datacenter chips.

All three core types and IP are ready to be licensed out to customers today to drop into their processors. ®

https://www.theregister.com//2024/08/13/akeana_riscv_cpus/